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si5504bdc www.vishay.com vishay siliconix s13-2463-rev. c, 02-dec-13 1 document number: 74483 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 n- and p-channel 30 v (d-s) mosfet marking code: ef ordering information: si5504bdc-t1-e3 (lead (pb)-free) si5504bdc-t1-ge3 (lead (p b)-free and ha logen-free) features ? trenchfet ? power mosfets ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ? dc/dc for portable applications ?load switch notes a. package limited. b. surface mounted on 1" x 1" fr4 board. c. t = 5 s. d. see reliability manual for profile. the chipfet is a leadless package. the end of the lead te rminal is exposed copper (not pl ated) as a result of the singulation process in manufacturing. a solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequade bottom side so lder interconnection. e. rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. maximum under steady stat e conditions is 120 c/w. product summary v ds (v) r ds(on) ( ? )i d (a) q g (typ.) n-channel 30 0.065 at v gs = 10 v 4 a 2 nc 0.100 at v gs = 4.5 v 4 a p-channel -30 0.140 at v gs = -10 v -3.7 2.2 nc 0.235 at v gs = -4.5 v -2.8 1206-8 chipfet ? dual top view 1 1.8 mm 3.0 mm 1 1 1 8 m m 30 m m bottom view 2 g 1 3 s 2 4 g 2 1 s 1 d 1 7 d 2 6 d 2 5 d 1 8 available n-channel mosfet g 1 d 1 s 1 s 2 g 2 d 2 p-channel mosfet absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol n-channel p-channel unit drain-source voltage v ds 30 -30 v gate-source voltage v gs 20 continuous drain current (t j = 150 c) t c = 25 c i d 4 a -3.7 a t c = 85 c 3.8 -2.7 t a = 25 c 3.7 b,c -2.5 b,c t a = 85 c 2.6 b,c -1.8 b,c pulsed drain current i dm 10 -10 source drain current diode current t c = 25 c i s 2.5 -2.5 t a = 25 c 1.3 b,c -1.3 b,c maximum power dissipation t c = 25 c p d 3.12 3.1 w t c = 85 c 2 2 t a = 25 c 1.5 b,c 1.5 b,c t a = 85 c 0.8 b,c 0.8 b,c operating junction and storage temperature range t j , t stg -55 to 150 c soldering recommendations (peak temperature) d,e 260 thermal resistance ratings parameter symbol n-channel p-channel unit typ. max. typ. max. maximum junction-to-ambient b,f t ? 5 s r thja 70 85 70 85 c/w maximum junction-to-foot (drain) steady state r thjf 33 40 33 40
si5504bdc www.vishay.com vishay siliconix s13-2463-rev. c, 02-dec-13 2 document number: 74483 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. guaranteed by design, not su bject to production testing. b. pulse test; pulse width ? 300 s, duty cycle ? 2 %. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a n-ch 30 - - v v gs = 0 v, i d = -250 a p-ch -30 - - v ds temperature coefficient ? v ds /t j i d = 250 a n-ch - 27 - mv/c i d = -250 a p-ch - -30 - v gs(th) temperature coefficient ? v gs(th) /t j i d = 250 a n-ch - -5 - i d = -250 a p-ch - 3.5 - gate threshold voltage v gs(th) v ds = v gs , i d = 250 a n-ch 1.5 - 3 v v ds = v gs , i d = -250 a p-ch -1.5 - -3 gate-body leakage i gss v ds = 0 v, v gs = 20 v n-ch - - 100 na p-ch - - -100 zero gate voltage drain current i dss v ds = 30 v, v gs = 0 v n-ch - - 1 a v ds = -30 v, v gs = 0 v p-ch - - -1 v ds = 30 v, v gs = 0 v, t j = 85 c n-ch - - 5 v ds = -30 v, v gs = 0 v, t j = 85 c p-ch - - -5 on-state drain current b i d(on) v ds ? 5 v, v gs = 10 v n-ch 10 - - a v ds ? -5 v, v gs = -10 v p-ch -10 - - drain-source on-s tate resistance b r ds(on) v gs = 10 v, i d = 3.1 a n-ch - 0.053 0.065 ? v gs = -10 v, i d = -2.1 a p-ch - 0.112 0.140 v gs = 4.5 v, i d = 1 a n-ch - 0.081 0.100 v gs = -4.5 v, i d = -0.43 a p-ch - 0.188 0.235 forward transconductance b g fs v ds = 15 v, i d = 3.1 a n-ch - 5 - s v ds = -15 v, i d = -2.1 a p-ch - 3.5 - dynamic a input capacitance c iss n-channel v ds = 15 v, v gs = 0 v, f = 1 mhz p-channel v ds = -15 v, v gs = 0 v, f = 1 mhz n-ch - 220 - pf p-ch - 170 - output capacitance c oss n-ch - 50 - p-ch - 50 - reverse transfer capacitance c rss n-ch - 25 - p-ch - 31 - total gate charge q g v ds = 15 v, v gs = 10 v, i d = 3.6 a n-ch - 4.5 7 nc v ds = -15 v, v gs = -10 v, i d = -2.5 a p-ch - 4.5 7 n-channel v ds = 15 v, v gs = 4.5 v, i d = 3.6 a p-channel v ds = -15 v, v gs = -4.5 v, i d = -2.5 a n-ch - 2 3 p-ch - 2.2 3.5 gate-source charge q gs n-ch - 0.7 - p-ch - 0.7 - gate-drain charge q gd n-ch - 0.7 - p-ch - 1 - gate resistance r g f = 1 mhz n-ch - 3 - ? p-ch - 13 -
si5504bdc www.vishay.com vishay siliconix s13-2463-rev. c, 02-dec-13 3 document number: 74483 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. guaranteed by design, not su bject to production testing. b. pulse test; pulse width ? 300 s, duty cycle ? 2 %. stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit dynamic a turn-on delay time t d(on) n-channel v dd = 15 v, r l = 5.8 ? i d ? 2.6 a, v gen = 4.5 v, r g = 1 ? p-channel v dd = -15 v, r l = 7.5 ? i d ? -2 a, v gen = -4.5 v, r g = 1 ? n-ch - 15 25 ns p-ch - 30 45 rise time t r n-ch - 80 120 p-ch - 60 90 turn-off delay time t d(off) n-ch - 12 20 p-ch - 10 15 fall time t f n-ch - 25 40 p-ch - 10 15 turn-on delay time t d(on) n-channel v dd = 15 v, r l = 5.8 ? i d ? 2.6 a, v gen = 10 v, r g = 1 ? p-channel v dd = -15 v, r l = 7.5 ? i d ? -2 a, v gen = -10 v, r g = 1 ? n-ch - 4 8 p-ch - 4 8 rise time t r n-ch - 12 20 p-ch - 10 15 turn-off delay time t d(off) n-ch - 10 15 p-ch - 10 15 fall time t f n-ch - 5 10 p-ch - 5 10 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c n-ch - - 2.5 a p-ch - - -2.5 pulse diode forward current a i sm n-ch - - 10 p-ch - - -10 body diode voltage v sd i s = 2.6 a, v gs = 0 v n-ch - 0.8 1.2 v i s = -2 a, v gs = 0 v p-ch - -0.8 -1.2 body diode reverse recovery time t rr n-channel i f = 2.6 a, di/dt = 100 a/s, t j = 25 c p-channel i f = -2 a, di/dt = -100 a/s, t j = 25 c n-ch - 30 50 ns p-ch - 20 40 body diode reverse recovery charge q rr n-ch - 20 40 nc p-ch - 10 20 reverse recovery fall time t a n-ch - 23 - ns p-ch - 13 - reverse recovery rise time t b n-ch - 7 - p-ch - 7 -
si5504bdc www.vishay.com vishay siliconix s13-2463-rev. c, 02-dec-13 4 document number: 74483 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 n-channel typical characteristics (25 c, unless otherwise noted) output characteristics on-resistance vs. drain current gate charge transfer characteristics capacitance on-resistance vs. junction temperature 0 4 8 12 16 20 0.0 0.5 1.0 1.5 2.0 2.5 v gs = 10 v thru 6 v 3 v v ds - drain-to-source voltage (v) - drain current (a) i d 4 v 5 v - on-resistance ( ) r ds(on) 0.00 0.04 0.08 0.12 0.16 0.20 0 5 10 15 20 i d - drain current (a) v gs = 4.5 v v gs = 10 v 0 2 4 6 8 10 012345 v ds = 15 v, i d - gate-to-source voltage (v) q g - total gate charge (nc) v gs v ds = 24 v, i d = 3.6 a = 3.6 a 0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 t c = 125 c t c = 25 c v gs - gate-to-source voltage (v) - drain current (a) i d t c = - 55 c 0 50 100 150 200 250 300 0 5 10 15 20 25 30 v ds - drain-to-source voltage (v) c rss c oss c iss c - capacitance (pf) 0.6 0.8 1.0 1.2 1.4 1.6 1.8 - 50 - 25 0 25 50 75 100 125 150 v gs = 10 v, 4.5 v i d = 3.1 a t j - junction temperature (c) (normalized) - on-resistance r ds(on)
si5504bdc www.vishay.com vishay siliconix s13-2463-rev. c, 02-dec-13 5 document number: 74483 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 n-channel typical characteristics (25 c, unless otherwise noted) source-drain diode forward voltage threshold voltage on-resistance vs. gate-to-source voltage single pulse power safe operating area, junction-to-ambient 0.0 0.2 0.4 0.6 0.8 1.0 1.2 t j = 150 c t j = 25 c 1 v sd ) v ( e g a t l o v n i a r d - o t - e c r u o s - - source current (a) i s 10 1.2 1.4 1.6 1.8 2.0 2.2 2.4 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a (v) v gs(th) t j - temperature (c) 0.04 0.08 0.12 0.16 0.20 0246810 i d = 3.1 a - on-resistance ( ) r ds(on) v gs - gate-to-source voltage (v) 25 c 125 c 0.001 0 1 50 10 30 10 0.01 power (w) time (s) 20 40 0.1 100 1000 0.0001 - drain current (a) i d 1 0.01 100 1 0.1 0.01 0.1 10 t a = 25 c single pulse 10 ms 1 s, 10 s dc 100 s 10 1 ms v ds - drain-to-source voltage (v) * v gs minimum v gs at which r ds(on) is specified limited by r * ds(on) 100 ms bvdss limited
si5504bdc www.vishay.com vishay siliconix s13-2463-rev. c, 02-dec-13 6 document number: 74483 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 n-channel typical characteristics (25 c, unless otherwise noted) current derating* power derating * the power dissipation p d is based on t (max.) = 150 c, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determine the cu rrent rating, when this rating falls below the package limit. 0 1 2 3 4 5 6 0 25 50 75 100 125 150 i d - drain current (a) t c - case temperature (c) package limited 0 1 2 3 4 25 50 75 100 125 150 t c - case temperature (c) power dissipation (w)
si5504bdc www.vishay.com vishay siliconix s13-2463-rev. c, 02-dec-13 7 document number: 74483 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 n-channel typical characteristics (25 c, unless otherwise noted) normalized thermal transient impedance, junction-to-ambient normalized thermal transient impedance, junction-to-foot square wave pulse duration (s) normalized ef fective transient thermal impedance 2 1 0.1 0.01 10 -3 10 -2 0 0 6 0 1 1 10 -1 10 -4 duty cycle = 0.5 0.2 0.1 0.05 0.02 single pulse 100 1. duty cycle, d = 2. per unit base = r thja = 1 00 c/w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 notes: 4. surface mounted p dm 10 -3 10 -2 0 1 1 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single pulse duty cycle = 0.5 square wave pulse duration (s) normalized effective transient thermal impedance
si5504bdc www.vishay.com vishay siliconix s13-2463-rev. c, 02-dec-13 8 document number: 74483 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 p-channel typical characteristics (25 c, unless otherwise noted) output characteristics on-resistance vs. drain current gate charge transfer characteristics capacitance on-resistance vs. junction temperature 0 2 4 6 8 10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v gs = 10 v thru 5 v v ds - drain-to-source voltage (v) - drain current (a) i d 3 v 4 v - on-resistance ( ) r ds(on) 0.0 0.1 0.2 0.3 0.4 0246810 i d - drain current (a) v gs = 10 v v gs = 4.5 v 0 2 4 6 8 10 012345 i d = 2.5 a - gate-to-so urce voltage (v) q g - total gate charge (nc) v gs v ds = 15 v v ds = 24 v 0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 t c = 125 c 25 c v gs - gate-to-source voltage (v) - drain current (a) i d - 55 c 0 50 100 150 200 250 0 5 10 15 20 25 30 v ds - drain-to-source voltage (v) c - capacitance (pf) c oss c iss c rss 0.6 0.8 1.0 1.2 1.4 1.6 1.8 - 50 - 25 0 25 50 75 100 125 150 v gs = 4.5 v, 10 v i d = 2.2 a t j - junction temperature (c) r ds(on) - on-resistance (normalized)
si5504bdc www.vishay.com vishay siliconix s13-2463-rev. c, 02-dec-13 9 document number: 74483 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 p-channel typical characteristics (25 c, unless otherwise noted) source-drain diode forward voltage threshold voltage on-resistance vs. gate-to-source voltage single pulse power safe operating area, junction-to-ambient 0.0 0.2 0.4 0.6 0.8 1.0 1.2 t j = 150 c t j = 25 c 10 1 v sd ) v ( e g a t l o v n i a r d - o t - e c r u o s - - source current (a) i s 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a (v) v gs(th) t j - temperature (c) 0.0 0.1 0.2 0.3 0.4 246810 i d = 2.2 a - on-resistance ( ) r ds(on) v gs - gate-to-source voltage (v) 125 c 25 c 0.001 0 1 50 10 30 10 0.01 power (w) time (s) 20 40 0.1 100 1000 0.0001 0.01 v ds - drain-to-source voltage (v) * v gs minimum v gs at which r ds(on) is specified - drain c urrent (a) i d 10 0.1 0.1 1 10 limited by r * ds(on) 1 t a = 25 c single pulse 100 ms 1 s, 10 s dc 100 s 100 10 ms 0.01 1 ms bvdss limited
si5504bdc www.vishay.com vishay siliconix s13-2463-rev. c, 02-dec-13 10 document number: 74483 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 p-channel typical characteristics (25 c, unless otherwise noted) current derating* power derating * the power dissipation p d is based on t j(max.) = 150 c, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determine the cu rrent rating, when this rating falls below the package limit. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 25 50 75 100 125 150 t c - case temperature (c) i d - drain current (a) 0 1 2 3 4 25 50 75 100 125 150 t c - case temperature (c) power dissipation (w)
si5504bdc www.vishay.com vishay siliconix s13-2463-rev. c, 02-dec-13 11 document number: 74483 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 p-channel typical characteristics (25 c, unless otherwise noted) normalized thermal transient impedance, junction-to-ambient normalized thermal transient impedance, junction-to-foot vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?74483 . square wave pulse duration (s) normalized effe ctive transient thermal impedance 2 1 0.1 0.01 10 -3 10 -2 0 0 6 0 1 1 10 -1 10 -4 duty cycle = 0.5 0.2 0.1 0.05 0.02 single pulse 100 1. duty cycle, d = 2. per unit base = r thja = 100 c/w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 notes: 4. surface mounted p dm 10 -3 10 -2 0 1 1 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single pulse duty cycle = 0.5 square wave pulse duration (s) normalized ef fective transient thermal impedance
package information vishay siliconix document number: 71151 15-jan-04 www.vishay.com 1 1206-8 chipfet c e e 1 e d a 65 7 8 34 2 1 4 l 5678 4321 4 s b 2x 0.10/0.13 r backside view x notes: 1. all dimensions are in millimeaters. 2. mold gate burrs shall not exceed 0.13 mm per side. 3. leadframe to molded body offset is horizontal and vertical shall not exceed 0.08 mm. 4. dimensions exclusive of mold gate burrs. 5. no mold flash allowed on the top and bottom lead surface. detail x c1 millimeters inches dim min nom max min nom max a 1.00 ? 1.10 0.039 ? 0.043 b 0.25 0.30 0.35 0.010 0.012 0.014 c 0.1 0.15 0.20 0.004 0.006 0.008 c1 0 ? 0.038 0 ? 0.0015 d 2.95 3.05 3.10 0.116 0.120 0.122 e 1.825 1.90 1.975 0.072 0.075 0.078 e 1 1.55 1.65 1.70 0.061 0.065 0.067 e 0.65 bsc 0.0256 bsc l 0.28 ? 0.42 0.011 ? 0.017 s 0.55 bsc 0.022 bsc 5 nom 5 nom ecn: c-03528?rev. f, 19-jan-04 dwg: 5547
an812 vishay siliconix document number: 71127 12-dec-03 www.vishay.com 1 dual-channel 1206-8 chipfet power mosfet recommended pad pattern and thermal performance introduction new vishay siliconix chipfets in the leadless 1206-8 package feature the same outline as popular 1206-8 resistors and capacitors but provide all the performance of true power semiconductor devices. the 1206-8 chipfet has the same footprint as the body of the little foot tsop-6, and can be thought of as a leadless tsop-6 for purposes of visualizing board area, but its thermal performance bears comparison with the much larger so-8. this technical note discusses the dual chipfet 1206-8 pin-out, package outline, pad patterns, evaluation board layout, and thermal performance. pin-out figure 1 shows the pin-out description and pin 1 identification for the dual-channel 1206-8 chipfet device. the pin-out is similar to the tsop-6 configuration, with two additional drain pins to enhance power dissipation and thus thermal performance. the legs of the device are very short, again helping to reduce the thermal path to the external heatsink/pcb and allowing a larger die to be fitted in the device if necessary. figure 1. dual 1206-8 chipfet s 1 g 1 s 2 d 1 d 1 d 2 g 2 d 2 for package dimensions see the 1206-8 chipfet package outline drawing ( http://www.vishay.com/doc?71151 ). basic pad patterns the basic pad layout with dimensions is shown in application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfet s, ( http://www.vishay.com/doc?72286 ). this is sufficient for low power dissipation mosfet applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. figure 2. footprint with copper spreading 80 mil 43 mil 10 mil 26 mil 18 mil 25 mil the pad pattern with copper spreading shown in figure 2 improves the thermal area of the drain connections (pins 5 and 6, pins 7 and 8) while remaining within the confines of the basic footprint. the drain copper area is 0.0019 sq. in. or 1.22 sq. mm. this will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the dual device. the addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. an example of this method is implemented on the vishay siliconix evaluation board described in the next section (figure 3). the vishay siliconix evaluation board for the dual 1206-8 the dual chipfet 1206-08 evaluation board measures 0.6 in by 0.5 in. its copper pad pattern consists of an increased pad area around each of the two drain leads on the top-side? approximately 0.0246 sq. in. or 15.87 sq. mm?and vias added through to the underside of the board, again with a maximized copper pad area of approximately the board-size dimensions, split into two for each of the drains. the outer package outline is for the 8-pin dip, which will allow test sockets to be used to assist in testing. the thermal performance of the 1206-8 on this board has been measured with the results following on the next page. the testing included comparison with the minimum recommended footprint on the evaluation board-size pcb and the industry standard one-inch square fr4 pcb with copper on both sides of the board.
an812 vishay siliconix www.vishay.com 2 document number: 71127 12-dec-03 front of board back of board figure 3. vishay.com chipfet thermal performance junction-to-foot thermal resistance (the package performance) thermal performance for the 1206-8 chipfet measured as junction-to-foot thermal resistance is 30 c/w typical, 40 c/w maximum for the dual device. the ?foot? is the drain lead of the device as it connects with the body. this is identical to the dual so-8 package r jf performance, a feat made possible by shortening the leads to the point where they become only a small part of the total footprint area. junction-to-ambient thermal resistance (dependent on pcb size) the typical r ja for the dual-channel 1206-8 chipfet is 90 c/w steady state, identical to the so-8. maximum ratings are 110 c/w for both the 1206-8 and the so-8. both packages have comparable thermal performance on the 1? square pcb footprint with the 1206-8 dual package having a quarter of the body area, a significant factor when considering board area. testing to aid comparison further, figure 4 illustrates chipfet 1206-8 dual thermal performance on two different board sizes and three different pad patterns.the results display the thermal performance out to steady state and produce a graphic account on how an increased copper pad area for the drain connections can enhance thermal performance. the measured steady state values of r ja for the dual 1206-8 chipfet are : 1) minimum recommended pad pattern (see figure 2) on the evaluation board size of 0.5 in x 0.6 in. 185 c/w 2) the evaluation board with the pad pattern described on figure 3. 128 c/w 3) industry standard 1? square pcb with maximum copper both sides. 90 c/w the results show that a major reduction can be made in the thermal resistance by increasing the copper drain area. in this example, a 57 c/w reduction was achieved without having to increase the size of the board. if increasing board size is an option, a further 38 c/w reduction was obtained by maximizing the copper from the drain on the larger 1? square pcb. time (secs) figure 4. dual 1206-8 chipfet thermal resistance (c/w) 0 1 200 40 80 100 1000 120 10 10 -1 10 -2 10 -3 10 -4 10 -5 1? square pcb dual evb min. footprint 160 summary the thermal results for the dual-channel 1206-8 chipfet package display identical power dissipation performance to the so-8 with a footprint reduction of 80%. careful design of the package has allowed for this performance to be achieved. the short leads allow the die size to be maximized and thermal resistance to be reduced within the confines of the tsop-6 body size. associated document 1206-8 chipfet single thermal performance, an811, (http://www.vishay.com/doc?71126) .
application note 826 vishay siliconix www.vishay.com document number: 72593 2 revision: 21-jan-08 application note recommended minimum pads for 1206-8 chipfet ? 0.080 (2.032) recommended mi nimum pads dimensions in inches/(mm) 0.093 (2.357) 0.036 (0.914) 0.022 (0.559) 0.026 (0.650) 0.016 (0.406) 0.010 (0.244) return to index return to index
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